Phase-locked-loop with VCO
Courtesy/Thanks to: Philips Semiconductor
Description: The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT4046A are phase-locked-loop circuits that comprise a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3) with a common signal input amplifier and a common comparator input.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the “4046A” forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required.
The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input (COMPIN), or connected via a frequency-divider. The VCO output signal has a duty factor of 50% (maximum expected deviation 1%), if the VCO input is held at a constant DC level. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption.
The only difference between the HC and HCT versions is the input level specification of the INH input. This input disables the VCO section. The sections of the comparator are identical, so that there is no difference in the SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC and HCT versions.
The signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range.
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