A logic analyzer using the PCs parallel port
Open Source DIY logic analyzer
Courtesy/Thanks to: JWA Systems
Description: A logic analyzer is useful in electronic development and debugging, especially where fast logic circuits are involved with lots of signals whose relations have to be verified or examined.
A logic analizer is a like a recorder for digital signals. During a certain (small) period of time, the state of a few digital lines can be recorded to a file. An event can be specified to signal the start of the recording, i.e. line 1 toggeling from 0 to 1.
This recording can be viewed afterwards, allowing for zooming and scrolling in the time domain.
In this page a homebuilt logic analizer is presented.
This logic analyzer can:
Run on Win95 and Win98 and ME using non-interrupted burst acquisition.
Run on Win2000 NT XP with interrupted acquisition, using the allowio driver.
Support ECP parallel ports.
Record up to 8 channels.
Use any parallel port.
Sampling at up to 1 million samples per second, depending on your hardware.
Record 32768 samples.
Save and load recordings to/from disk
Use an "Advanced Trigger" sceme. It waits for a channel to remain stable for a given time (Delay), and then it starts sampling after the first change of that channel.
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